The invention may be applied particularly to the construction of control members of microprogrammed digital computers.
In known apparatus, determining the address of the next microinstruction in a sequence of microinstructions is performed in two sequential stages which involve: (1) testing a specific part of the microinstruction, then (2) selectively branching to a branch address contained in the microinstruction, or (3) incrementing the content of an address counter by one unit if the address of the next microinstruction directly follows the microinstruction currently being executed. To be more exact, the prior art requires at least three sequential orders within a microinstruction cycle to define two calculation stages. The orders require a branch register to be loaded, or an address counter to be incremented. The determination of which order is to be executed is dictated by testing one or more conditions which are stored in indicators. The order is made when the preceding microinstruction has been completely executed. The microinstruction register is loaded with a microinstruction read from memory at an address given by the branch register or the instruction counter. The indicators are loaded at the end of the microinstruction cycle. To define a microinstruction cycle it is necessary to consider the two preceding microinstruction determination stages and to allow each of these a tolerance for its duration. Irreducible tolerances for the duration of the microinstruction cycles are provided primarily for the response times of the electronic components involved in each of the two stages.
An object of the present invention is to provide a method of and apparatus for determining microinstruction addresses more rapidly than do prior art arrangements.
Another object of the invention is to provide a new and improved apparatus for and method of determining the address of the next microinstruction in a sequence of microinstructions.